My design has a 48-bit time count, and the resolution of the count will be 10 CLOCKs, so 48 bits feels not very good to split. Now I want to compare the 48-bit count with the total count. With XST synthesis, there are too many stages and the speed can't come up.
Is there any way to optimize the code, can you increase the speed?
always@(posedge clk_in)
begin
if(Tcmp> total_clk_cal)begin
CLK_tmp <= total_clock-cur_clk;
end
else begin
CLK_tmp <= Tn_1- Tlast;
end
end
All the variables are all register output. There is a strong correlation between input and output, this timing is just not very good to split, but also by the multi-stage pipeline. I wanted to see if there is a more efficient algorithm for comparing the size.
The current processing is to forcibly add a level of pipeline, the logic of other parts have been adjusted, and I always feel uncomfortable.
