Can I use VERILOG to write TB to test VHDL code?

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  Jack Posted on 2020/7/4 11:54:25

  The vhdl verilog module can be called by each other.

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  Gaby Posted on 2020/7/4 14:06:52

  can.

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  Lance Posted on 2020/7/4 20:54:53

  Thanks, because many instances are written in VHDL, and I don't want to use VHDL, so I have always been worried about this. Thank you upstairs.

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