rt, the input is five 8bit data in parallel. When the data changes and is not 0, each data (8bit is regarded as a whole) is serially output to fifo. How to design to output the data in the least time period?
Author: tomasz pindar Jul 03, 2020 1484
rt, the input is five 8bit data in parallel. When the data changes and is not 0, each data (8bit is regarded as a whole) is serially output to fifo. How to design to output the data in the least time period?
Nicholas Posted on 2020/7/4 14:04:27
Can it be made clearer?
1. Serial, does it mean byte order or a string of beads?
2. The fastest, does it refer to input FIFO or output from FIFO?
However, asking and talking are basically nonsense. From judging the condition to sending it into the FIFO, one clock can be completed;
From the FIFO output, one clock goes one level.
Reply 0
Nick Posted on 2020/7/4 20:52:03
The process of judging the data change and not 0 is pure combinational logic.
Not much to say about FIFO, it can be regarded as nothing here.
If the conditions are met, the process of selecting data and sending out is started.
One always @ (clk) can be achieved.
Reply 0Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: CPLDs
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: Embedded - CPLDs (Complex Programmable Logic Devices)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Unconfirmed -
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Support
