The first
reg aa;
wire aa_rising;
wire aa_falling;
always @(posedge sys_clk)
begin
if(rst_l==1'b0)
begin
aa_r<=1'b0;
end
else if(bb==1'b0)
aa_r<=aa;
end
assign aa_rising = (aa_r==1'b0 && (aa==1'b1))?1'b1:1'b0;
assign aa_falling=(aa_r==1'b1 && (aa==1'b0))?1'b1:1'b0;
Normal image
The second
reg [3:0] aa;
wire aa_rising;
wire aa_falling;
always @(posedge sys_clk)
begin
if(rst_l==1'b0)
begin
aa_r<=4'd0;
end
else if(bb==1'b0)
aa_r[3:0]<={aa[2:0],aa};
end
assign aa_rising = (aa_r==4'b0011)?1'b1:1'b0;
assign aa_falling=(aa_r==4'b1100)?1'b1:1'b0;
Image is messy
The clock is 125M
Which help explain what is wrong with these two writing styles
