How to extract the pulse edges in multiple cycles separately under CLK?

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  Gabriel Posted on 2020/7/4 11:44:07

  This is the most basic thing in FPGA, search online. Lots of ready-made code.

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  Dennis Posted on 2020/7/4 11:44:38

  Continuous sampling, put into the array,

  After the wave pushes forward, only the latest two are saved;

  At the same time, 01 is the rising edge and 10 is the falling edge.

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• 

  Dennis Posted on 2020/7/4 13:55:10

  This is easy to handle, first count the edges, and then assign the corresponding edges to different OUTs according to different count values.

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  Brandon Posted on 2020/7/4 20:45:00

  Shift register! Along the edge, if it is judged as 01, the value will be assigned, and it will decrease to 0, and the output judgment will be greater than 0 and output high level.

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