Compilation is a problem, please take a look, did not know what went wrong after changing it several times? Thank you?
Error (10170): Verilog HDL syntax error at Verilog1.v(12) near text "always"; expecting "@", or an identifier ("always" is a reserved keyword ).
module srcn(pd,nc1,i1,j1);
input clk,rst_n;
reg[63:0] sc1,ac1,tc,tc1,s1;
reg[63:0] pd [1:510][1:510];
reg[31:0] nq[0:1];
integer i1,j1;
initial
always @(posedge clk or negedge rst_n)
begin
for(i=1;i<511;i=i+1)
begin
for(j=1;j<511;j=j+1)
begin
ac1=64'b0;
tc=64'b0;
sc1=64'b0;
for(k=0;k<=2;k=k+1)
begin
for(l=0;l<=2;l=l+1)
begin
ac1=ac1+pd[i+k][j+l];
end
end
for(k=0;k<=2;k=k+1)
begin
for(l=0;l<=2;l=l+1)
begin
tc1=pd[i+k][j+l]-ac1;
tc=tc+pd[i+k][j+l]*tc1;
end
end
s1=tc/9;
sc1=s1^0.5;
if(sc1<1.5)
begin
nq[0] = nq[0]+1;
end
else
begin
nq[1] = nq[1]+1;
end
end
end
end
endmodule
This is the code written.
