moduledisplay_control(clk,clk_1Hz,reset,key,sw,state,hour,min,temh,teml,humh,huml,en,led_time);
input clk,clk_1Hz;
input reset;
input [3:0] key;
input sw;
output [3:0] state;
output [7:0] hour,min;
output [7:0] temh,teml;
output [7:0] humh,huml;
output en;
output led_time;
reg [3:0] state;
reg [7:0] hour,min;
reg [7:0] temh,teml;
reg [7:0] humh,huml;
reg en;
reg led_time;
reg clk_min;
reg [7:0] clk_cnt;
parameter rst_hour = 8’H01;
parameter rst_min = 8’H00;
parameter rst_temh = 8’H25;
parameter rst_teml = 8’H20;
parameter rst_humh = 8’H65;
parameter rst_huml = 8’H55;
always @(posedge clk_1Hz or posedgereset)
if(reset)
clk_cnt <= 0;
else if(sw)
if(clk_cnt < 29)
clk_cnt <=clk_cnt + 1;
else
begin
clk_cnt <= 0;
clk_min <=~clk_min;
end
always @(posedge key[3] or posedge key[2]or posedge reset)
if(reset)
state <= 0;
else if(key[3])
state <= 0;
else if(key[2])
if(state <= 12)
state <= state +1;
else
state <= 0;
always @(posedge clk_min or posedgekey[1] or posedge key[0] or negedge sw or posedge reset)
if(reset)
begin
hour <= rst_hour;
min <= rst_min;
en <= 1;
end
else if(!sw)
begin
en <= 1;
led_time <= 0;
if(key[1])
case(state)
10: if(min[3:0] == 9) min[3:0]<= 0;
elsemin[3:0] <= min[3:0]+1;
11: if(min[7:4] == 9) min[7:4]<= 0;
elsemin[7:4] <= min[7:4]+1;
12: if(hour[3:0] == 9) hour[3:0]<= 0;
elsehour[3:0] <= hour[3:0]+1;
13: if(hour[7:4] == 9) hour[7:4]<= 0;
elsehour[7:4] <= hour[7:4]+1;
default: ;
endcase
else if(key[0])
case(state)
10: if(min[3:0] == 0) min[3:0]<= 9;
elsemin[3:0] <= min[3:0]-1;
11: if(min[7:4] == 0) min[7:4]<= 9;
elsemin[7:4] <= min[7:4]-1;
12: if(hour[3:0] == 0) hour[3:0]<= 9;
elsehour[3:0] <= hour[3:0]-1;
13: if(hour[7:4] == 0) hour[7:4]<= 9;
elsehour[7:4] <= hour[7:4]-1;
default: ;
endcase
end
else if(clk_min)
begin
led_time <= clk_1Hz;
if(min[3:0] == 0)
if(min[7:4] == 0)
if(hour[3:0]== 0)
if(hour[7:4]== 0)
begin
hour<= rst_hour;
min<= rst_min;
en<= 0;
end
else
begin
hour[7:4]<= hour[7:4]-1;
hour[3:0]<= 9;
min[7:4]<= 5;
min[3:0]<= 9;
end
else
begin
hour[3:0]<= hour[3:0]-1;
min[7:4]<= 5;
min[3:0]<= 9;
end
else
begin
min[7:4]<= min[7:4]-1;
min[3:0]<= 9;
end
else
min[3:0] <=min[3:0]-1;
end
always @(posedge key[1] or posedge key[0]or posedge reset)
if(reset)
begin
temh <= rst_temh;
teml <= rst_teml;
end
else if(key[1])
case(state)
6: if(teml[3:0] == 9) teml[3:0] <= 0;
elseteml[3:0] <= teml[3:0]+1;
7: if(teml[7:4] == 9) teml[7:4] <= 0;
elseteml[7:4] <= teml[7:4]+1;
8: if(temh[3:0] == 9) temh[3:0] <= 0;
elsetemh[3:0] <= temh[3:0]+1;
9: if(temh[7:4] == 9) temh[7:4] <= 0;
elsetemh[7:4] <= temh[7:4]+1;
default: ;
endcase
else if(key[0])
case(state)
6: if(teml[3:0] == 0) teml[3:0] <= 9;
elseteml[3:0] <= teml[3:0]-1;
7: if(teml[7:4] == 0) teml[7:4] <= 9;
elseteml[7:4] <= teml[7:4]-1;
8: if(temh[3:0] == 0) temh[3:0] <= 9;
elsetemh[3:0] <= temh[3:0]-1;
9: if(temh[7:4] == 0) temh[7:4] <= 9;
elsetemh[7:4] <= temh[7:4]-1;
default: ;
endcase
always @(posedge key[1] or posedge key[0]or posedge reset)
if(reset)
begin
humh <= rst_humh;
huml <= rst_huml;
end
else if(key[1])
case(state)
2: if(huml[3:0] == 9) huml[3:0] <= 0;
elsehuml[3:0] <= huml[3:0]+1;
3: if(huml[7:4] == 9) huml[7:4] <= 0;
elsehuml[7:4] <= huml[7:4]+1;
4: if(humh[3:0] == 9) humh[3:0] <= 0;
elsehumh[3:0] <= humh[3:0]+1;
5: if(humh[7:4] == 9) humh[7:4] <= 0;
elsehumh[7:4] <= humh[7:4]+1;
default: ;
endcase
else if(key[0])
case(state)
2: if(huml[3:0] == 0) huml[3:0] <= 9;
elsehuml[3:0] <= huml[3:0]-1;
3: if(huml[7:4] == 0) huml[7:4] <= 9;
elsehuml[7:4] <= huml[7:4]-1;
4: if(humh[3:0] == 0) humh[3:0] <= 9;
elsehumh[3:0] <= humh[3:0]-1;
5: if(humh[7:4] == 0) humh[7:4] <= 9;
elsehumh[7:4] <= humh[7:4]-1;
default: ;
endcase
endmodule
