As the title, test function: judge the signal change and count.
Be puzzled, ask the master to answer.
The code in test bench is as follows:
always @(posedge Bus2IP_Clk) begin
if(m_axi_mm2s_arready&m_axi_mm2s_arvalid)begin
m_axi_mm2s_rvalid = 1; //Already initialized to 0 in the initialization module
end //Change = to <= then the simulation result test bench and the count in uut are consistent
else if(sendok) begin
m_axi_mm2s_rvalid = 0;
end
end
reg [4:0] testnum;
always @(posedge Bus2IP_Clk) begin
if(m_axi_mm2s_rvalid)begin //It has been initialized to 0 in the initialization module
testnum <= testnum + 1;
end
end
In project engineering, but the code called by the test bench instantiated by uut, where all values except testc are passed in from the test bench
always @(posedge Bus2IP_Clk)
begin
if( Bus2IP_Resetn == 1'b0)
begin
testc <= 0;
end
else if(m_axi_mm2s_rvalid)
begin
testc <= testc +1;
end
end
The simulation picture is:
In the test bench, the count will be one cycle ahead of time. If you change = to <=, the simulation result will be the same on both sides.
Seek to explain! !
