The FPGA board currently designed uses the FPGA model XC7Z100-FFG900. A problem occurred recently during the joint debugging with the customer. The FPGA has several GPIOs connected to the customer board through connectors. The corresponding pins on the customer board Long-term 3.3V high state. After connecting to the GPIO of our board, our FPGA cannot be loaded normally, and the GPIO pins are directly connected from the FPGA to the inter-board connector. Disconnecting the connector returns to normal. After testing, it is found that due to the high level of the GPIO link peer, our GPIO corresponding to the VCCO33 of BANK is pulled up to about 2.1V. In theory, the INPUT pin of the FPGA is in a high-impedance state, I don’t know why this happens In this scenario, I found several single boards and tried them out, all of which had this problem.

Please refer to the schematic diagram. In fact, GPIO is directly pulled from the FPGA to the inter-board connector, and there is no other connection.