The younger brother’s subject needs to be something similar to a camera. The temporarily determined solution is STM32F4 as the processor, CPLD drives the CCD, the image resolution is 795*596, and the CCD signal acquisition processing chip AD9840A parallelizes the image signal in the form of 10-bit. Passed out, put into SRAM by CPLD,
My question now is I don’t know how to combine STM32, CPLD, and SRAM organically. CPLD puts the CCD signal into SRAM, and then STM32 has to read data from SRAM. How should the relationship between them be coordinated? How should the address bus and data bus be allocated, and how to avoid conflicts when reading and writing? If you need to use two pieces of SRAM for ping-pong operation, how to deal with the data and address bus? Can you provide some reference for your brother, thank you!
