[TOP] So many IP cores already in existence, why still need to write HDL?
Posted by tomasz pindar · On Jun 17, 2020 at 19:32 PM
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[TOP] So many IP cores already in existence, why still need to write HDL?
Posted by tomasz pindar · On Jun 17, 2020 at 19:32 PM
4
13.4 version EDK download encountered problems with Data2MEM, seeking answers Urgent!
Posted by Jim.T · On Jul 08, 2020 at 12:04 PM
9
Modelsim simulation error problem.
Posted by Allen Chi · On Aug 18, 2020 at 22:00 PM
9
Why doesn't my counter count? Ask God to explain.
Posted by Meg Peng · On Jul 20, 2020 at 09:54 AM
8
GTX send and receive data simulation problem.
Posted by Natasha Tokatlian · On Jul 20, 2020 at 10:19 AM
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About PCI express link rate and width.
Posted by Sylvia · On Jul 23, 2020 at 12:25 PM
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Posted by Leon Hidalgo · On Jul 02, 2020 at 19:10 PM
8
The GPIO pin keeps the 3.3V high state on the board for a long time.
Posted by Stefan Andrey · On Jun 26, 2020 at 18:11 PM
6
How to simulate VHDL in modelsim.
Posted by Stefan Andrey · On Jul 23, 2020 at 12:07 PM
6
Can Virtex-6 be interconnected via PCI EXPRESS cable?
Posted by Luigi Iuliano · On Jul 14, 2020 at 09:34 AM
6
Posted by Michael Pinneke · On Oct 29, 2020 at 00:00 AM
6
May I ask the value of ref_timer counter in sdram?
Posted by Mark Arvin · On Aug 18, 2020 at 03:10 AM
6
How to convert mcs file to BIN file?
Posted by Ficken Bumsen · On Aug 14, 2020 at 19:11 PM
5
Why does SPI come up with these four modes?
Posted by Juan Hsiung · On Aug 17, 2020 at 09:21 AM
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Posted by jamie · On Aug 22, 2020 at 08:24 AM
5
Quartus II 11.0 cannot recognize USB Blaster.
Posted by Sylvia · On Nov 17, 2020 at 05:48 AM
5
Communication between FPGA and Labview.
Posted by Leon Hidalgo · On Dec 26, 2020 at 15:21 PM
5
Why does modelsim have different values before and after assignment?
Posted by Juan Hsiung · On Jul 20, 2020 at 10:12 AM
5
Problems with modelsim10.1d data stream window.
Posted by Jim.T · On Jul 20, 2020 at 10:39 AM
5
How to make modelsim simulate the xilinx primitive module?
Posted by Rodolfo Lehner · On Jul 20, 2020 at 11:25 AM
5
FPGA Spartan-IIE Family 50K Gates 1728 Cells 400MHz 0.15um Technology 1.8V 208-Pin PQFP
Xilinx QFP100
Xilinx TQFP44
FPGA Spartan-XL Family 5K Gates 238 Cells 217MHz 3.3V 84-Pin PLCC
FPGA Spartan Family 10K Gates 466 Cells 166MHz 5V 144-Pin TQFP EP
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