[TOP] So many IP cores already in existence, why still need to write HDL?
Posted by tomasz pindar · On Jun 17, 2020 at 19:32 PM
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[TOP] So many IP cores already in existence, why still need to write HDL?
Posted by tomasz pindar · On Jun 17, 2020 at 19:32 PM
9
13.4 version EDK download encountered problems with Data2MEM, seeking answers Urgent!
Posted by Jim.T · On Jul 08, 2020 at 12:04 PM
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Modelsim simulation error problem.
Posted by Allen Chi · On Aug 18, 2020 at 22:00 PM
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Why doesn't my counter count? Ask God to explain.
Posted by Meg Peng · On Jul 20, 2020 at 09:54 AM
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GTX send and receive data simulation problem.
Posted by Natasha Tokatlian · On Jul 20, 2020 at 10:19 AM
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About PCI express link rate and width.
Posted by Sylvia · On Jul 23, 2020 at 12:25 PM
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Posted by Leon Hidalgo · On Jul 02, 2020 at 19:10 PM
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What is the difference between Altera and lattice?
Posted by Stefan Andrey · On Nov 25, 2020 at 21:21 PM
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Posted by Michael Pinneke · On Oct 29, 2020 at 00:00 AM
6
May I ask the value of ref_timer counter in sdram?
Posted by Mark Arvin · On Aug 18, 2020 at 03:10 AM
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How to simulate VHDL in modelsim.
Posted by Stefan Andrey · On Jul 23, 2020 at 12:07 PM
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Can Virtex-6 be interconnected via PCI EXPRESS cable?
Posted by Luigi Iuliano · On Jul 14, 2020 at 09:34 AM
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The GPIO pin keeps the 3.3V high state on the board for a long time.
Posted by Stefan Andrey · On Jun 26, 2020 at 18:11 PM
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Why did SPI come up with these four modes?
Posted by Allen Chi · On Jun 26, 2020 at 17:04 PM
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What does CPLD rookie ask about this schematic?
Posted by DORIS · On Jul 05, 2020 at 10:42 AM
5
Consult the question about spartan-3an, how to write to the on-chip flash.
Posted by sonia touati · On Jul 05, 2020 at 11:23 AM
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How does FPGA receive LVDS signal?
Posted by Ficken Bumsen · On Jul 05, 2020 at 11:31 AM
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For help, SPARTAN 3E+AT45DB041D startup problem.
Posted by Stefan Andrey · On Jul 06, 2020 at 19:06 PM
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Why does modelsim have different values before and after assignment?
Posted by Juan Hsiung · On Jul 20, 2020 at 10:12 AM
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Problems with modelsim10.1d data stream window.
Posted by Jim.T · On Jul 20, 2020 at 10:39 AM
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FPGA Spartan-IIE Family 50K Gates 1728 Cells 400MHz 0.15um Technology 1.8V 208-Pin PQFP
Xilinx QFP100
Xilinx TQFP44
FPGA Spartan-XL Family 5K Gates 238 Cells 217MHz 3.3V 84-Pin PLCC
FPGA Spartan Family 10K Gates 466 Cells 166MHz 5V 144-Pin TQFP EP
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