[TOP] So many IP cores already in existence, why still need to write HDL?
Posted by tomasz pindar · On Jun 17, 2020 at 19:32 PM
4
[TOP] So many IP cores already in existence, why still need to write HDL?
Posted by tomasz pindar · On Jun 17, 2020 at 19:32 PM
4
Has anyone used the Labview FPGA Module?
Posted by Sylvia · On Dec 26, 2020 at 18:41 PM
4
Will CPU registers be pushed onto the stack when BX and BLX instructions are executed?
Posted by stephen david · On Dec 22, 2020 at 00:00 AM
1
What is the difference between Quartus prime and Quartus II?
Posted by Juan Hsiung · On Nov 11, 2020 at 07:10 AM
2
What is the difference between ZCU102, ZCU104 and ZCU106?
Posted by stephen david · On Nov 25, 2020 at 10:04 AM
1
Modelsim simulation error problem.
Posted by Allen Chi · On Aug 18, 2020 at 22:00 PM
9
Quartus II 11.0 cannot recognize USB Blaster.
Posted by Sylvia · On Nov 17, 2020 at 05:48 AM
5
Verilog implements floor, round rounding and saturation operations.
Posted by Juan Hsiung · On Jul 02, 2020 at 20:28 PM
1
Why does SPI come up with these four modes?
Posted by Juan Hsiung · On Aug 17, 2020 at 09:21 AM
5
Can Virtex-6 be interconnected via PCI EXPRESS cable?
Posted by Meg Peng · On Jul 23, 2020 at 14:54 PM
4
Ask about spartan 3 asynchronous fifo.
Posted by jamie · On Jul 07, 2020 at 10:50 AM
1
Assign an array to another array.
Posted by Ficken Bumsen · On Aug 03, 2020 at 09:54 AM
2
Xiaobai asks, serial port reception.
Posted by Jim.T · On Jun 26, 2020 at 13:44 PM
1
Ask: Who has used ODDR2 of xilinx?
Posted by Matteo Scalcione · On Jul 06, 2020 at 12:19 PM
3
About Labview FPGA programming issues.
Posted by Jim.T · On Dec 26, 2020 at 13:36 PM
3
Posted by Michael Pinneke · On Jun 26, 2020 at 13:42 PM
1
Vivado 2016.1 cannot run in ZC706?
Posted by Matteo Scalcione · On Nov 28, 2020 at 10:11 AM
1
Spartan 6 SPI Flash EOL replacement.
Posted by Rodolfo Lehner · On Nov 21, 2020 at 18:54 PM
3
Communication between FPGA and Labview.
Posted by Leon Hidalgo · On Dec 26, 2020 at 15:21 PM
5
How to realize FPGA synthesis of SoC verification platform?
Posted by Luigi Iuliano · On Dec 25, 2020 at 08:14 AM
3
FPGA Spartan-IIE Family 50K Gates 1728 Cells 400MHz 0.15um Technology 1.8V 208-Pin PQFP
Xilinx QFP100
Xilinx TQFP44
FPGA Spartan-XL Family 5K Gates 238 Cells 217MHz 3.3V 84-Pin PLCC
FPGA Spartan Family 10K Gates 466 Cells 166MHz 5V 144-Pin TQFP EP
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