[TOP] So many IP cores already in existence, why still need to write HDL?
Posted by tomasz pindar · On Jun 17, 2020 at 19:32 PM
4
[TOP] So many IP cores already in existence, why still need to write HDL?
Posted by tomasz pindar · On Jun 17, 2020 at 19:32 PM
4
Has anyone used the Labview FPGA Module?
Posted by Sylvia · On Dec 26, 2020 at 18:41 PM
4
Communication between FPGA and Labview.
Posted by Leon Hidalgo · On Dec 26, 2020 at 15:21 PM
5
About Labview FPGA programming issues.
Posted by Jim.T · On Dec 26, 2020 at 13:36 PM
3
How to realize FPGA synthesis of SoC verification platform?
Posted by Luigi Iuliano · On Dec 25, 2020 at 08:14 AM
3
What is the difference between SOC, MCU and FPGA?
Posted by Michael Pinneke · On Dec 24, 2020 at 08:58 AM
2
What are the functions of SoC FPGAs?
Posted by jamie · On Dec 23, 2020 at 00:00 AM
2
Will CPU registers be pushed onto the stack when BX and BLX instructions are executed?
Posted by stephen david · On Dec 22, 2020 at 00:00 AM
1
Is there a way to add Spartan 7 on Vivado?
Posted by Ficken Bumsen · On Dec 22, 2020 at 00:00 AM
3
Black screen when running Qt GUI on ZC706.
Posted by Mark Arvin · On Nov 29, 2020 at 10:30 AM
2
Vivado 2016.1 cannot run in ZC706?
Posted by Matteo Scalcione · On Nov 28, 2020 at 10:11 AM
1
How does PCI Express communicate between the zc706 board and the host PC.
Posted by Mark Arvin · On Nov 28, 2020 at 00:14 AM
0
The user manual details of the DE1 SoC Development Kit are free to download.
Posted by Allen Chi · On Nov 27, 2020 at 20:35 PM
0
Excuse me ZCU106: What should I do if SCUI cannot work normally?
Posted by Allen Chi · On Nov 27, 2020 at 17:38 PM
4
How to connect DE1-SoC and computer through Uart.
Posted by Jim.T · On Nov 27, 2020 at 17:24 PM
0
I want to set i2c2 in hps to FPGA io, but it can’t work normally The qsys settings are as follows:
Posted by Sylvia · On Nov 27, 2020 at 06:49 AM
0
What is the data format of ADC/DAC on ZCU111?
Posted by jamie · On Nov 26, 2020 at 11:04 AM
2
MAX II cpld and FT2232H+OpenOCD
Posted by stephen david · On Nov 25, 2020 at 22:00 PM
1
What is the difference between Altera and lattice?
Posted by Stefan Andrey · On Nov 25, 2020 at 21:21 PM
2
How to set arduino as a slave?
Posted by stephen david · On Nov 25, 2020 at 10:26 AM
3
FPGA Spartan-IIE Family 50K Gates 1728 Cells 400MHz 0.15um Technology 1.8V 208-Pin PQFP
Xilinx QFP100
Xilinx TQFP44
FPGA Spartan-XL Family 5K Gates 238 Cells 217MHz 3.3V 84-Pin PLCC
FPGA Spartan Family 10K Gates 466 Cells 166MHz 5V 144-Pin TQFP EP
Support
