Posted by Sylvia · On Aug 14, 2020 at 19:16 PM
0
Posted by Sylvia · On Aug 14, 2020 at 19:16 PM
0
How to convert mcs file to BIN file?
Posted by Ficken Bumsen · On Aug 14, 2020 at 19:11 PM
5
The data width does not match.
Posted by stephen david · On Aug 14, 2020 at 19:07 PM
4
Please help everyone, why the address is not output.
Posted by Stefan Andrey · On Aug 14, 2020 at 19:04 PM
1
Doubts about cardinality notation.
Posted by Philipp Zielinski · On Aug 14, 2020 at 18:55 PM
1
The problem of fpga multiple clock sources.
Posted by Rodolfo Lehner · On Aug 14, 2020 at 18:53 PM
0
The RAM module of the FPGA program cannot be used in one of the 100 motherboards.
Posted by zana villegas · On Aug 14, 2020 at 18:51 PM
0
How to make fonts in FPGA, ask for answers.
Posted by DORIS · On Aug 05, 2020 at 16:40 PM
3
Regarding the clock setting in timing analysis.
Posted by Juan Hsiung · On Aug 05, 2020 at 16:37 PM
3
How does xilinx fpga look at the number of multipliers?
Posted by Juan Hsiung · On Aug 05, 2020 at 16:23 PM
3
About 1.5v, 2.5v, 3.3v, 1.8v power supply bypass capacitors.
Posted by Natasha Tokatlian · On Aug 05, 2020 at 16:22 PM
1
Why can't my computer USB Blaster install! I have installed Quartus 9.0.
Posted by Matteo Scalcione · On Aug 05, 2020 at 16:19 PM
2
Ask about the SFP problem of ml505/ml507.
Posted by Mark Arvin · On Aug 05, 2020 at 16:13 PM
2
What is the difference between xilinx and ALTERA's FPGA development tools?
Posted by Jim.T · On Aug 05, 2020 at 16:09 PM
5
Novices ask, why does the input always change to zzzzzzzz when using ISim to simulate.
Posted by Allen Chi · On Aug 05, 2020 at 16:04 PM
4
Verilog assign keyword, can it be used like this?
Posted by sonia touati · On Aug 05, 2020 at 15:57 PM
5
The fpga count returns to 0 and there is an exception.
Posted by Allen Chi · On Aug 03, 2020 at 10:48 AM
2
Posted by sonia touati · On Aug 03, 2020 at 10:05 AM
1
Verilog implements cubic spline interpolation.
Posted by Michael Pinneke · On Aug 03, 2020 at 10:01 AM
5
All aspects of FPGA design need to be paid attention to.
Posted by jamie · On Aug 03, 2020 at 09:58 AM
0
FPGA Spartan-IIE Family 50K Gates 1728 Cells 400MHz 0.15um Technology 1.8V 208-Pin PQFP
Xilinx QFP100
Xilinx TQFP44
FPGA Spartan-XL Family 5K Gates 238 Cells 217MHz 3.3V 84-Pin PLCC
FPGA Spartan Family 10K Gates 466 Cells 166MHz 5V 144-Pin TQFP EP
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