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CPLD design Verilog routine frequency division counting experiment engineering file source code

Document Type: Source Code

Size: 192.06KB

Download Count: 94

Published time: 2020.07.03

Introduction

This experiment can be said to be the most basic experiment of verilog entry, we do not do too much theoretical points Analysis, practice is the last word. In the experiment, we connected the clk_div output signal and the buzzer to together, everyone can really feel what frequency division is.


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  • CPLD CoolRunner -II Family 3K Gates 128 Macro Cells 152MHz 0.18um Technology 1.8V Automotive 132-Pin CSBGA
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  • XA2C384-11TQG144Q

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  • CPLD CoolRunner -II Family 9K Gates 384 Macro Cells 118MHz 0.18um Technology 1.8V Automotive 144-Pin TQFP
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