TR5 FPGA Development Kit User Manual

The Terasic TR5 Stratix V GX FPGA Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth interface, ultra-low latency communication, high pin count, and power efficiency. With an iPass PCIe gen3 connector, the TR5 is designed for the most demanding high-end applications, empowered with the Altera 28 nm Stratix V GX, delivering the best system-level integration and flexibility in the industry.

The Stratix® V GX FPGA features integrated transceivers that transfer at a maximum of 12.5Gbps, this allows the TR5 to be fully compliant with version 3.0 of the PCI Express standard. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the TR5 delivers one independent bank of DDR3 SO-DIMM RAM, one ZBT SSRAM, and high-speed parallel flash memory. The feature set of the TR5 fully supports all high-intensity applications such as ASIC verification, data acquisition, and signal processing.