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FPGAKey Technical Documents
Download DatasheetThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX EPM7256EQI160-10N devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX architecture
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
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| Specification | Value |
|---|---|
| Series | MAX 7000 |
| Memory Type | EEPROM |
| Number of Macrocells | 256 |
| Maximum Operating Frequency | 90.9 MHz |
| Delay Time | 12 ns |
| Number of Programmable I/Os | 164 |
| Operating Supply Voltage | 5 V |
| Maximum Operating Temperature | + 70 C |
| Minimum Operating Temperature | 0 C |
| Package / Case | PGA-192 |
| Mounting Style | SMD/SMT |
| Packaging | Tray |
| Supply Voltage - Max | 5.25 V |
| Supply Voltage - Min | 4.75 V |
3+ $135.6810
5+ $133.7700
8+ $129.9480
20+ $127.0815
30+ $122.3040
150+ $119.4375
300+ $116.5710
3+ $150.8750
5+ $148.7500
8+ $144.5000
20+ $141.3125
30+ $136.0000
150+ $132.8125
300+ $129.6250
1+ $2,414.6300
5+ $2,213.4100
10+ $2,043.1500
25+ $1,770.7300
1+ $5,197.4500
1+ $129.5854
1+ $297.2100
10+ $237.7700
50+ $216.1500
100+ $198.1400
250+ $158.5100
500+ $148.6100
1000+ $139.8600
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