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FPGAKey Technical Documents
Download DatasheetMAX 7000B devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX EPM7256BTI100-7 devices operate with a 2.5-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 3.5 ns, and counter speeds up to 303.0 MHz.
■ High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture (see Table 1)
– Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families
– High-density PLDs ranging from 600 to 10,000 usable gates
– 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz
■ Advanced 2.5-V in-system programmability (ISP)
– Programs through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in-system programming
– ISP circuitry compliant with IEEE Std. 1532
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Specification | Value |
---|---|
Series | MAX 7000 |
Memory Type | EEPROM |
Number of Macrocells | 256 |
Maximum Operating Frequency | 172.4 MHz |
Delay Time | 5.5 ns |
Number of Programmable I/Os | 164 |
Operating Supply Voltage | 3.3 V |
Maximum Operating Temperature | + 70 C |
Minimum Operating Temperature | 0 C |
Package / Case | FBGA-256 |
Mounting Style | SMD/SMT |
Packaging | Tray |
Supply Voltage - Max | 3.6 V |
Supply Voltage - Min | 3 V |
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