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Download DatasheetThe EPM7128SLC84-20 of MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. EPM7128SLC84-20 devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P.
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
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Specification | Value |
---|---|
Series | MAX 7000 |
Memory Type | EEPROM |
Number of Macrocells | 128 |
Maximum Operating Frequency | 192.3 MHz |
Delay Time | 5 ns |
Number of Programmable I/Os | 68 |
Operating Supply Voltage | 3.3 V |
Maximum Operating Temperature | + 70 C |
Minimum Operating Temperature | 0 C |
Package / Case | PLCC-84 |
Mounting Style | SMD/SMT |
Packaging | Tube |
Supply Voltage - Max | 3.6 V |
Supply Voltage - Min | 3 V |
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