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Download DatasheetThe EPM7032TC44-24 devices are MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades.
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
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Specification | Value |
---|---|
Series | MAX 7000 |
Memory Type | EEPROM |
Number of Macrocells | 32 |
Maximum Operating Frequency | 227.3 MHz |
Delay Time | 4.5 ns |
Number of Programmable I/Os | 36 |
Operating Supply Voltage | 3.3 V |
Maximum Operating Temperature | + 70 C |
Minimum Operating Temperature | 0 C |
Package / Case | PLCC-44 |
Mounting Style | SMD/SMT |
Packaging | Tube |
Supply Voltage - Max | 3.6 V |
Supply Voltage - Min | 3 V |
80+ $4.4872
90+ $4.4240
170+ $4.2976
400+ $4.2028
800+ $4.0448
4000+ $3.9500
8000+ $3.8552
1+ $2.795
1+ $2.795
390+ $5.1952
390+ $5.1952
1+ $2.4100
1+ $2.4100
1+ $4.4800
1+ $75.1172
5+ $75.0713
20+ $75.0283
50+ $74.9853
100+ $74.9437
1+ $75.1172
5+ $75.0713
20+ $75.0283
50+ $74.9853
100+ $74.9437
26+ $74.723
26+ $74.723
1+ $3.5983
5+ $3.55
20+ $3.5047
50+ $3.4594
100+ $3.4156
120+ $4.4800
1+ $3.2726
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