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Download DatasheetThe EPM7032SLC44-6F PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7032SLC44-6F provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades.
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
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Specification | Value |
---|---|
Programmable Type | In System Programmable |
Delay Time tpd(1) Max | 5.0ns |
Voltage Supply - Internal | 4.75V ~ 5.25V |
Number of Logic Elements/Blocks | 2 |
Number of Macrocells | 32 |
Number of Gates | 600 |
Number of I/O | 36 |
Operating Temperature | 0??C ~ 70??C (TA) |
Mounting Type | Surface Mount |
Package / Case | 44-LCC (J-Lead) |
Supplier Device Package | 44-PLCC (16.58x16.58) |
CPLD MAX 7000S Family 600 Gates 32 Macro Cells 142.9MHz 5V 44-Pin PLCC Tube
CPLD MAX 7000S Family 600 Gates 32 Macro Cells 175.4MHz 5V 44-Pin PLCC Tray
CPLD MAX 7000 Family 600 Gates 32 Macro Cells 142.9MHz 5V 44-Pin PLCC Tray
CPLD MAX 7000S Family 600 Gates 32 Macro Cells 116.3MHz 5V 44-Pin PLCC Tube
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210+ $15.4112
1100+ $15.0500
2100+ $14.6888
21+ $17.0968
30+ $16.8560
50+ $16.3744
110+ $16.0132
210+ $15.4112
1100+ $15.0500
2100+ $14.6888
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160+ $20.3648
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21+ $17.0968
30+ $16.8560
50+ $16.3744
110+ $16.0132
210+ $15.4112
1100+ $15.0500
2100+ $14.6888
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