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Download DatasheetEPM7032BLC44-3N devices are high-density, high-performance devices based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000B devices operate with a 2.5-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 3.5 ns, and counter speeds up to 303.0 MHz.
The EPM7032BLC44-3N architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. The MAX 7000 architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. EPM7032BLC44-3N devices are available in a wide range of packages, including PLCC, PGA, PQFP, RQFP, and TQFP packages.
■ High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture (see Table 1)
– Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families
– High-density PLDs ranging from 600 to 10,000 usable gates
– 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz
■ Advanced 2.5-V in-system programmability (ISP)
– Programs through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in-system programming
– ISP circuitry compliant with IEEE Std. 1532
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Specification | Value |
---|---|
Programmable Type | In System Programmable |
Delay Time tpd(1) Max | 3.5ns |
Voltage Supply - Internal | 2.375V ~ 2.625V |
Number of Logic Elements/Blocks | 2 |
Number of Macrocells | 32 |
Number of Gates | 600 |
Number of I/O | 36 |
Operating Temperature | 0??C ~ 70??C (TA) |
Mounting Type | Surface Mount |
Package / Case | 44-LCC (J-Lead) |
Supplier Device Package | 44-PLCC (16.58x16.58) |
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