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Download DatasheetMAX 5000 Erasable Programmable Logic Devices (EPLDs) represent a revolutionary step in programmable logic: they combine innovative architecture and state-of-the-art process to offer optimum performance, logic density, flexibility, and the highest speeds and densities available in general-purpose reprogrammable logic. These EPLDs are high-speed, high-density replacements for Ss1 and MSI TTL and CMOS packages and conventional PLDs. For example, an EPM5192LI-2 replaces over 100 7400 series SSI and MSI TTL and CMOS packages, integrating complete subsystems into a single package, saving board area, and reducing power consumption.
Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.
The advanced MAX 5000 architecture combines the speed, ease of use,and familiarity of PAL devices with the density of programmable gate arrays.
MAX 5000 EPLDs provide 15-ns combinatorial delays, counter frequencies up to 100 MHz, pipelined data rates of 100 MHz, and high-complexity designs with true system clock rates up to 66 MHz.
Available in a wide variety of packages, including DIP, SOIC, J-lead, PGA, and QFP formats in windowed ceramic and plastic one-time-programmable versions.
MAX+PLUS and MAX+PLUS II PC- and workstation-based development tools compile large designs in minutes.
An industry-standard EDIF interface to workstation and third-party CAE tools is available.
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| Specification | Value |
|---|---|
| Macrocells | 192 |
| Maximum Flip-Flops | 252 |
| Maximum Latches | 384 |
| Pins | 100/84 |
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