EPM5130LC-1 of Altera MAX 5000 Devices

EPM5130LC-1 FPGAs Overview

MAX 5000 EPLDs use CMOS EPROM cells to configure logic functions within the devices. The EPM5130LC-1 device architecture is user-configurable to accommodate a variety of independent logic functions, and the EPLDs can be erased for quick and efficient iterations during design development and debug cycles.

The EPM5130LC-1 of MAX 5000 Erasable Programmable Logic Devices（EPLDs）represent a revolutionary step in programmable logic:they combine innovative architecture and state-of-the-art process to offer optimum performance，logic density，flexibility，and the highest speeds and densities available in general-purpose reprogrammable logic.These EPLDs are high-speed，high-

density replacements for SSI and MSI TTL and CMOS packages and conventional PLDs.For example，an EPM5192 replaces over 100 7400-series SSI and MSI TTL and CMOS packages，integrating complete subsystems into a single package，saving board area，and reducing power consumption.

Features

Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.
The advanced MAX 5000 architecture combines the speed, ease of use, and familiarity of PAL devices with the density of programmable gate arrays.
MAX 5000 EPLDs provide 15-ns combinatorial delays, counter frequencies up to 100 MHz, pipelined data rates of 100 MHz, and high-complexity designs with true system clock rates up to 66 MHz. Available in a wide variety of packages, including DIP, SOIC,J-lead, PGA, and QFP formats in windowed ceramic and plastic one-time-programmable versions.
MAX+PLUS and MAX+PLUS II PC-and workstation-based development tools compile large designs in minutes.
An industry-standard EDIF interface to workstation and third-party CAE tools is available.

口Multiple Array MatriX（MAX）5000 architecture solves speed，density，and design flexibility problems

-Advanced macrocell array provides registered，combinatorial，or flow-through latch operation.

-Expander product-term array automatically provides additional combinatorial or registered logic.

-Decoupled I/O block with dual feedback on I/O pins allows flexible pin utilization.

Programmable Interconnect Array（PIA）provides automatic 100%

routing in devices with multiple LABs.

Each macrocell supports combinatorial and registered operation，using single or multiple clocks within a single EPLD.

口MAX5000 Performance

-Pipelined data rates up to 100 MHz

-Counters as fast as 100 MHz tpp performance from 15 ns to 25ns

-Advanced 0.8-micron CMOS EPROM technology口MAX5000 Logic Density

-16-to 192-macrocell devices

20to 100-pin packages

32 to 384 flip-fiops and latches More than 32 product terms on a single macrocell

-Product-term expansion on any data or control path口MAX+PLUS&MAX+PLUS II Design Tools

-Design entry via unified，hierarchical schematic capture，Altera Hardware Description Language（AHDL），and waveform design entry（waveform entry in MAX+PLUS II only）

Fast，automatic design processing with logic synthesis Automatic design partitioning into multiple EPLDs

（MAX+PLUS II only）

-Automatic device fitting，no hand-editing needed-Hardware and software design verification tools口 EDIF interface to MAX+PLUS&MAX+PLUS II provides paths to Viewlogic Systems，Valid Logic Systems，Mentor Graphics，and other workstation-based CAE tools.

FAQ

Q: Does the price of EPM5130LC-1 devices fluctuate frequently?
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Q: How can I obtain software development tools related to the Altera FPGA platform?
Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Altera EPM5130 Development Boards, Evaluation Boards, or MAX 5000 EPLD Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain EPM5130LC-1 technical support documents?
Enter the "EPM5130LC-1" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: What should I do if I did not receive the technical support for EPM5130LC1 in time?
Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the EPM5130LC-1 pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.