EPM3512AQC208-7/I208-10

Features

■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming                                                

FAQ

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• Q: How can I obtain software development tools related to the Altera FPGA platform?
• Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
• Q: Where can I purchase Altera EPM3512A Development Boards, Evaluation Boards, or MAX 3000A Starter Kit? also provide technical information?
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• Q: How to obtain EPM3512AQC208-7/I208-10 technical support documents?
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• Q: What should I do if I did not receive the technical support for EPM3512AQC2087I20810 in time?
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