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FPGAKey Technical Documents
Download DatasheetAltera’s Flexible Logic Element MatriX (FLEX) EPF81188ARC2405 combines the benefits of both erasable programmable logic devices (EPLDs) and fieldprogrammable gate arrays (FPGAs). The FLEX 8000 EPF81188ARC2405 device s ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources.
FLEX 8000 EPF81188ARC2405 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers. The high-pin-count packages can integrate multiple 32-bit buses into a single device.
The logic and interconnections in the FLEX 8000 architecture are configured with CMOS SRAM elements. FLEX 8000 EPF81188ARC2405 devices are configured at system power-up with data stored in an industry-standard parallel EPROM or an Altera serial configuration devices, or with data provided by a system controller. Altera offers the EPC1, EPC1213, EPC1064, and EPC1441 configuration devices, which configure FLEX EPF81188ARC2405 devices via a serial data stream. Configuration data can also be stored in an industry-standard 32 K × 8 bit or larger configuration device, or downloaded from system RAM.
■ Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1)
– 2,500 to 16,000 usable gates
– 282 to 1,500 registers
■ System-level features
– In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller
– Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation
– Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
– MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels
– Low power consumption (typical specification is 0.5 mA or less in standby mode)
■ Flexible interconnect
– FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions)
– Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions)
– Tri-state emulation that implements internal tri-state nets
■ Powerful I/O pins
■ Programmable output slew-rate control reduces switching noise
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
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Industrial Control
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Medical Equipment
| Specification | Value |
|---|---|
| Number of LABs/CLBs | 126 |
| Number of Logic Elements/Cells | 1008 |
| Number of I/O | 184 |
| Number of Gates | 12000 |
| Voltage - Supply | 4.75V ~ 5.25V |
| Mounting Type | Surface Mount |
| Operating Temperature | 0??C ~ 70??C (TA) |
| Package / Case | 240-BFQFP Exposed Pad |
| Supplier Device Package | 240-RQFP (32x32) |
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