EP910JC-80 of Altera Classic EPLD Family

EP910JC-80 FPGAs Overview

The Altera Classic TM EP910JC-80 device offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet.

EP910JC-80 devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including ceramic dual in-line package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages.

EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications.

EP910JC-80 devices are 100% generically tested devices in windowed packages and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly.

Features

■ High-performance, 16-macrocell Classic EPLD

– Combinatorial speeds with tPD as fast as 10 ns

– Counter frequencies of up to 100 MHz

– Pipelined data rates of up to 125 MHz

■ Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins

■ EP610 and EP610I devices are pin-, function-, and programming file-compatible

■ Programmable clock option for independent clocking of all registers

■ Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation

■ Available in the following packages (see Figure 7):

– 24-pin small-outline integrated circuit (plastic SOIC only)

– 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP)

– 28-pin plastic J-lead chip carrier (PLCC)

FAQ

Q: Does the price of EP910JC-80 devices fluctuate frequently?
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Q: How can I obtain software development tools related to the Altera FPGA platform?
Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Altera EP910 Development Boards, Evaluation Boards, or Classic EPLD Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain EP910JC-80 technical support documents?
Enter the "EP910JC-80" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: What should I do if I did not receive the technical support for EP910JC80 in time?
Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the EP910JC-80 pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.