This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > FPGA Familis > Classic EPLD Family > EP610SC-20
EP610SC-20

Images are for reference only.

EP610SC-20

Get Latest Price >

$64.001 - $74.493 | 1 Pieces(Min. Order)

Manufacturer:
Altera
Package/Case:
SOP-24
RoHS:
No RoHS
Lifecycle:
-
Stock Resource:
Factory Excess Stock / Franchised Distributor
Product Categories:
Classic EPLD Family
Description:
CPLD Classic Family 16 Macro Cells 62.5MHz 5V 24-Pin SOP
Do you want to buy more and get a better price for EP610SC-20? Please fill in the short form below:
quantity
email
contact
company
content

EP610SC-20 FPGAs Overview

The Altera ClassicTM EP610SC-20 device offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology, EP610SC-20 devices also have a Turbo-only version, which is described in this data sheet.

Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including ceramic dual in-line package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages.

EP610SC-20 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins, and 2 global clock pins. Each macrocell can access signals from the global bus, which consists of the true and complement forms of
the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The
CLK1 signal is a dedicated global clock input for the registers in macrocells 9 through 16. The CLK2 signal is a dedicated global clock input for registers in macrocells 1 through 8.

EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications.

Classic devices are 100% generically tested devices in windowed packages and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly. Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AND/fixed-OR structure that can implement logic with up to eight product terms. The programmable register can be individually programmed for D, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Altera’s proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to implement a variety of logic functions simultaneously.

Classic devices are supported by Altera’s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and workstationbased EDA tools. The MAX+PLUS II software runs on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow.

Features

High-performance, 16-macrocell Classic EPLD
– Combinatorial speeds with
tPD as fast as 10 ns
– Counter frequencies of up to 100 MHz
– Pipelined data rates of up to 125 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins
EP610 and EP610I devices are pin-, function-, and programming file-compatible
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation
Available in the following packages (see Figure 7):
– 24-pin small-outline integrated circuit (plastic SOIC only)
– 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP)
– 28-pin plastic J-lead chip carrier (PLCC)


FAQ

  • Q: Does the price of EP610SC-20 devices fluctuate frequently?
  • The FPGAkey search engine monitors the EP610SC-20 inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
  • Q: Do I have to sign up on the website to make an inquiry for EP610SC-20?
  • No, only submit the quantity, email address and other contact information required for the inquiry of EP610SC-20, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the Altera FPGA platform?
  • Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Altera EP610 Development Boards, Evaluation Boards, or Classic EPLD Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain EP610SC-20 technical support documents?
  • Enter the "EP610SC-20" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for EP610SC20 in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the EP610SC-20 pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Documents

Circuit Diagram

EP610
EP610

EP610SC-20 PDF Preview

EP610SC-20 Tags

  • Altera EP610
  • EP610 development board
  • Classic EPLD evaluation kit
  • Altera Classic EPLD development board
  • Classic EPLD starter kit
  • Classic EPLD EP610
  • EP610 reference design
  • EP610 evaluation board
  • EP610SC-20 Datasheet PDF

Other Authorized Distributors (Fpgakey will provide Competitive price from all franchised resource.)

  • DISTRIBUTOR
  • PART NUMBER
  • MANUFACTURER
  • DESCRIPTION
  • STOCK
  • PRICE
  • BUY
  • avnet
  • EP610SC-20
  • Rochester Electronics LLC
  • 0
  • 5+ $74.4932
    7+ $73.4440
    20+ $71.3456
    30+ $69.7718
    50+ $67.1488
    250+ $65.5750
    500+ $64.0012

Need Help?

Support

If you have any questions about the product and related issues, Please contact us.