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Home > FPGA Familis > Stratix II FPGA > EP2S60F1020

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$1035.005 - $2099 | 1 Pieces(Min. Order)





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Stratix II FPGA

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EP2S60F1020 FPGAs Overview

The Stratix II EP2S60F1020 FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of on-chip, TriMatrix memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions. Various high-speed external memory interfaces are supported, including double data rate (DDR) SDRAM and DDR2 SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data rate (SDR) SDRAM. Stratix II EP2S60F1020 devices support various I/O standards along with support for 1-gigabit per second (Gbps) source synchronous signaling with DPA circuitry. Stratix II devices offer a complete clock management solution with internal clock frequency of up to 550 MHz and up to 12 phase-locked loops (PLLs). Stratix II EP2S60F1020 devices are also the industry’s first FPGAs with the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm to protect designs.


The Stratix II family offers the following features:

■ New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency

■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources

■ TriMatrixmemory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers

■ High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters

■ Up to 16 global clocks with 24 clocking resources per device region

■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode

■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting


  • Q: Does the price of EP2S60F1020 devices fluctuate frequently?
  • The FPGAkey search engine monitors the EP2S60F1020 inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
  • Q: Do I have to sign up on the website to make an inquiry for EP2S60F1020?
  • No, only submit the quantity, email address and other contact information required for the inquiry of EP2S60F1020, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the Altera FPGA platform?
  • Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Altera EP2S60 Development Boards, Evaluation Boards, or Stratix II FPGA Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain EP2S60F1020 technical support documents?
  • Enter the "EP2S60F1020" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for EP2S60F1020 in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the EP2S60F1020 pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Attributes

  • Series

    Stratix II

  • Number of Logic Blocks


  • Number of I/Os


  • Operating Supply Voltage

    1.2 V to 3.3 V

  • Maximum Operating Temperature

    + 70 C

  • Mounting Style


  • Package / Case


  • Distributed RAM

    2.5 Mbit

  • Minimum Operating Temperature

    0 C

  • Operating Supply Current

    0.5 A

  • Packaging


Technical Documents

EP2S60F1020 PDF Preview

EP2S60F1020 Tags

  • Altera EP2S60
  • EP2S60 development board
  • Stratix II FPGA evaluation kit
  • Altera Stratix II FPGA development board
  • Stratix II FPGA starter kit
  • Stratix II FPGA EP2S60
  • EP2S60 reference design
  • EP2S60 evaluation board
  • EP2S60F1020 Datasheet PDF

Other Authorized Distributors (Fpgakey will provide Competitive price from all franchised resource.)

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  • 1+ $1138.5025

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  • EP2S60F1020C5N
  • IC FPGA 718 I/O 1020FBGA
  • 0
  • 1+ $1035.0046

  • digikey
  • EP2S60F1020I4
  • IC FPGA 718 I/O 1020FBGA
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  • 1+ $1821.6004

  • digikey
  • EP2S60F1020I4N
  • IC FPGA 718 I/O 1020FBGA
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  • 1+ $1656.0088

  • mouser
  • EP2S60F1020C4N
  • Altera Corporation
  • FPGA - Field Programmable Gate Array FPGA - Stratix II 3022 LABs 718 IOs
  • 2
  • 1+ $1,617.1800

  • verical
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  • Intel
  • 0
  • 1+ $1,293.7500

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