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FPGAKey Technical Documents
Download DatasheetThe Arria EP2AGX65CU1713N is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power, programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express (PCIe), Ethernet, and DDR3 memory are easily implemented in your design with the Quartus II software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera. The Arria II EP2AGX65CU1713N device makes designing for applications requiring transceivers operating at up to 6.375 Gbps fast and easy.
The Arria II device features consist of the following highlights:
■ 40-nm, low-power FPGA engine
■ Adaptive logic module (ALM) offers the highest logic efficiency in the industry
■ Eight-input fracturable look-up table (LUT)
■ Memory logic array blocks (MLABs) for efficient implementation of small FIFOs
■ High-performance digital signal processing (DSP) blocks up to 550 MHz
■ Configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers as well as 18 x 36-bit high-precision multiplier
■ Hardcoded adders, subtractors, accumulators, and summation functions
■ Fully-integrated design flow with the MATLAB and DSP Builder software from Altera
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
Specification | Value |
---|---|
Series | Arria II GX |
Number of Logic Blocks | 2530 |
Embedded Block RAM - EBR | 4455 Kbit |
Number of I/Os | 156 |
Maximum Operating Frequency | 390 MHz |
Operating Supply Voltage | 1.5 V to 3.3 V |
Maximum Operating Temperature | + 70 C |
Mounting Style | SMD/SMT |
Package / Case | BGA-358 |
Minimum Operating Temperature | 0 C |
Packaging | Tray |
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