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Altera MAX 7000 CPLD


The MAX 7000 CPLD family of high-density, high-performance PLDs is based on Altera‚Äôs second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. 

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MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest.

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MAX 7000 CPLD Devices

MAX 7000 CPLD Documents

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