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Altera MAX 10 CPLDs

MAX 10 CPLDs

Intel® MAX® 10 FPGAs revolutionize non-volatile integration by delivering advanced processing capabilities in a low-cost, single chip small form factor programmable logic device. Building upon the single chip heritage of previous MAX device families, densities range from 2K – 50K LEs, using either single or dual-core voltage supplies. The MAX 10 FPGA family encompasses both advanced small wafer scale packaging (3 mm x 3 mm) and high I/O pin count packages offerings.

MAX 10 FPGAs are built on TSMC’s 55 nm embedded NOR flash technology, enabling instant-on functionality. Integrated features include analog-to-digital converters (ADCs) and dual configuration flash allowing you to store and dynamically switch between two images on a single chip. Unlike CPLDs, MAX 10 FPGAs also include full-featured FPGA capabilities, such as Nios® II soft core embedded processor support, digital signal processing (DSP) blocks, and soft DDR3 memory controllers.

MAX 10 FPGAs offer system-level cost savings through increased integration of system component functions:

  • Dual configuration flash—A single, on-die flash memory supports dual configuration, for true fail-safe upgrades with thousands of possible reprogram cycles.

  • Analog blocks—Integrated analog blocks with ADCs and temperature sensor provide lower latency and reduced board space with more flexible sample-sequencing.

  • Instant on—MAX 10 FPGAs can be the first usable device on a system board to control bring-up of other components such as high density FPGAs, ASICs, ASSPs, and processors.

  • Nios® II soft core embedded processor—MAX 10 FPGAs support the integration of the soft core Nios II embedded processors, providing embedded developers a single-chip, fully configurable, instant-on processor subsystem.

  • DSP blocks—As the first non-volatile FPGA with DSP, MAX 10 FPGAs are ideal for high-performance, high-precision applications using integrated 18x18 multipliers.

  • DDR3 external memory interfaces—MAX 10 FPGAs support DDR3 SDRAM and LPDDR2 interfaces through soft intellectual property (IP) memory controllers, optimal for video, datapath, and embedded applications.

  • Complex control management—Software-controlled system management through Nios II soft core embedded processors

  • Single-core voltage support—Single supply offering required for power-up sequence management

  • User flash—With up to 736 KB of on-die user flash code storage, MAX 10 FPGAs enable advanced single chip Nios II embedded applications. The amount of user flash available depends on configuration options.

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