This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > FPGA Familis > Altera Classic EPLD Family

Altera

Altera Classic EPLD Family

Classic EPLD Family

The EP1830 is a fast, low-power version of the EP1810 device. This device can implement four 12-bit counters at up to 50 MHz and typically consumes 20mA when operating at 1 MHz. It is available with a maximum tep values of 20 ns and 25ns.


FPGA Documents

Need Help?

Support

If you have any questions about the product and related issues, Please contact us.