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FPGAKey Technical Documents
Download DatasheetAC22iHD1000-F45C3ES device run at a maximum rate of 750 MHz and have effective densities of up to one million LUTs. Based on the Intel 22nm process, AC22iHD1000-F45C3ES device is SRAM based and fully reconfigurable. Logic resources are provided using standard, synchronous, 4‐input LUTs. A reconfigurable logic block (RLB) contains ten LUTs, and has ten registers. AC22iHD1000-F45C3ES device also contain block RAMs. Each block RAM is 80 kb in size and allows true dual port access.
The I/O frame contains embedded controller IP, configurable I/O, SerDes, clock generator blocks with phase lock loops (PLLs), and the device configuration logic. AC22iHD1000-F45C3ES contain up to sixty‐four lanes of 10.3125 Gbps SerDes and up to an additional 960 high‐speed reconfigurable I/O. Additional dedicated hard IP includes up to six DDR2/3 PHY and controllers, up to forty eight 10 Gb Ethernet controllers, up to twelve 40G Ethernet controllers and up to four 100G Ethernet controllers. There are also are up to four Interlaken controllers and two PCI Express controllers, all available as embedded hard IP and therefore use none of the reconfigurable logic fabric and achieve maximum performance without the need for timing closure/optimization.
There are also dedicated I/O for the embedded programming and configuration logic (CFG) designed to support a variety of programming options. Dedicated clock I/O pins are located near the corners of each Speedster device.
FPGA Core The core of an Achronix AC22iHD1000-F45C3ES contain columns of logic, memory and multiplier/accumulators (BMACs) connected with a global interconnect as shown in figure 2 below. Columns of reconfigurable logic blocks (RLBs) are interspersed with columns of block RAMs (BRAMs) and local RAMs (LRAMs) and BMACs. The core also includes global and local clock networks as well as reset networks.
• Advanced highest‐density and highest‐bandwidth FPGA
Abundant embedded hard IP for communications applications
Fully re‐programmable, SRAM based
Synchronous core and I/O
Built on Intel’s advanced 22‐nm 3‐D Tri‐Gate process technology
• Large capacity
Up to 1 million effective look‐up‐tables
Up to 82 Mb of block RAM
80 Kb block RAMs running at 750 MHz
640 bit logic RAM (LRAM) running at 750 MHz
• Industry‐standard register transfer level (RTL) syn‐ thesis support using Synplify‐Pro from Synopsys
Rapid timing closure yielding significant time‐to‐market advantages Embedded (hard IP)
10/40/100 Gigabit Ethernet MAC
PCI Express Gen 1/2/3, ×1, ×4, ×8 with DMAengine
DDR 2/3 72 bits wide
Interlaken
• Up to 64 channels of embedded 10.3125 Gbps Ser‐Des:
PCI Express Gen 1/2/3
10/40/100 Gigabit Ethernet (XFI, XAUI, XLAUI,CAUI)
Interlaken
Fibre Channel
SATA/SAS
OC48
CEI‐6 SR/LR, CEI‐11 SR
GPON/EPON
CPRI/OBSAI
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
Specification | Value |
---|---|
Logic capacity with embedded IP (effective LUTs) | 1,045,000 |
Programmable LUTs | 700,000 |
Number of BRAM Instances | 1,026 |
Number of LRAM Instances | 6,156 |
80 Kb BRAM (total Kb) | 82,080 |
640-bit LRAM (total Kb) | 3,940 |
Multiplier/accumulators (BMACs) | 756 |
SerDes Lanes 10.3125 Gbps | 64 |
10G Ethernet MAC | 24 |
40G Ethernet MAC | 6 |
100G Ethernet MAC | 2 |
Interlaken LLC | 2 |
PCI Express LLC | 2 |
DDR3/DDR2 controller | 6 |
Number of PLLs | 16 |
User (programmable) I/O | 960 |
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