The Speedster7t FPGA family is optimized for high-bandwidth workloads and eliminates the performance bottlenecks associated with traditional FPGAs. Built on TSMC’s 7nm FinFET process, Speedster7t FPGAs feature a revolutionary new 2D network-on-chip (NoC), an array of new machine learning processors (MLPs) optimized for high-bandwidth and artificial intelligence/machine learning (AI/ML) workloads, high-bandwidth GDDR6 interfaces, 400G Ethernet and PCI Express Gen5 ports — all interconnected to deliver ASIC-level performance while retaining the full programmability of FPGAs. Get started today with the VectorPath accelerator card, featuring the Speedster7t FPGA.
Achronix’s new, high-performance, 7nm Speedster 7t FPGA family is specifically designed to support extremely high bandwidth requirements for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center.
Several performance criteria characterize these data-center and networking workloads:
The ability to handle high-speed data rates from a host processor’s PCIe port and up to 400 Gbps Ethernet ports.
The ability to store multiple gigabytes of incoming data and to access that data quickly for processing within the FPGA.
The ability to move massive amounts of data among the FPGA’s I/O ports, its internal memory, attached external memory, and its on-chip computing resources.
The ability to process high computational loads with tera-operations-per-second of performance.
The Speedster7t FPGA family can more than satisfy each of these performance criteria with appropriately scaled and optimized on-chip resources.
For data-center and networking applications, high-speed data enters an FPGA-based processing node in two fundamental ways: through PCIe connections to a host processor and via high-speed Ethernet connections to other data-center resources. The Speedster7t family is designed to maximize data rates over these connections by implementing a number of PCIe Gen5 interfaces for the host-processor connection(s) and multiple SerDes ports capable of supporting 400 Gbps Ethernet connections. Both of these I/O standards represent the fastest, most recent specifications for inter- and intra-system data communications used in data centers and myriad other FPGA-based applications. The Speedster7t FPGA’s multiple, high-speed I/O ports support data rates that data centers expect to see in the near future.
Most FPGAs store data that must be accessed quickly in on-chip SRAM. The Speedster7t FPGA family is no exception, incorporating a substantial amount of memory. However, the sheer volume of data that must be handled by many data-center applications almost universally overwhelms any available amount of on-chip SRAM, even when the FPGA in question is fabricated with 7nm FinFET process technology.
Consequently, the Speedster7t is designed with multiple GDDR6 graphics SDRAM ports. In the immediate future, GDDR6 SDRAMs will provide the fastest SDRAM access speeds with the lowest DRAM cost (per stored bit), at power levels equivalent to LPDDR5 SDRAM. Together, these characteristics make GDDR6 SDRAM interfaces the best choice for next-generation system designs. Members of the Speedster7t family support as many as eight independent GDDR6 memory ports.